A POWER service layer (PSL) unit of a Coherent Accelerator Process Interface (CAPI) device has at least three separate read/write data interfaces, one towards its internal cache, one towards the accelerator it is servicing, and one towards the link between the PSL device and the POWER processor chip. Various types of commands typically involve different read and write operations involving different ones of these read/write data interfaces and having different clock cycle latencies between them. Current approaches for executing such commands may result in a command having to wait to be processed until a previous command requiring one or more of the same interfaces has been processed.